For the purpose of repairing faulty memory cells, integrated memories generally have redundant units of memory cells which can replace normal units of memory cells containing faulty memory cells on an address basis. The redundant units of memory cells are, for example, in the form of redundant word lines or redundant bit lines which can replace normal word lines or normal bit lines. In this context, the integrated memory is tested using an external testing device or a self-test device, for example, and the redundant elements are then programmed. A redundancy circuit has programmable elements, for example, in the form of laser fuses or electrically programmable fuses, which are used to store the address of a unit which needs to be replaced. These programmable elements are programmed by means of a laser beam or by a “burning voltage”, for example, in the course of the memory's production process.
During operation of a memory of this type, faulty normal units, which need to be replaced, are replaced on an address basis by appropriate redundant units in the course of a memory access operation. Before a memory access operation, a redundancy evaluation is made in the redundancy circuits within a selected memory area. This is done by applying an address for the selected normal unit to an address bus and then comparing the applied address with an address for a faulty normal unit, which is stored in the respective redundancy circuit. If there is a match, the appropriate redundancy circuit activates the associated redundant unit instead of the faulty normal unit.
Integrated memories are generally subject to extensive function tests in the production process. These function tests are used, inter alia, to identify faulty memory cells or faulty word lines or bit lines. Function tests are also carried out on memories which have already been used in the application and in which faults have been found during operation of the memory. In such cases, it is desirable to carry out fault analysis in order to be able to gain further knowledge of physical relationships and failure probabilities.
One cause of varying fault behavior resides, for example, in the fact that the “data background” of certain memory cells differs depending on the memory. Faulty memory cells may, in particular, be physically adjacent to redundant units. In this case, a factor influencing the fault behavior of the memory cells in the immediate vicinity of redundant elements is whether one or more of the adjacent redundant elements are being used, i.e., have been programmed for a replacement operation for normal units (and thus have been topologically defined). Information of this type has hitherto not been available when analyzing a closed memory chip which has already been used in the application, since the original fault analysis data which was obtained by function tests in the production process is no longer available. In order, nevertheless, to make it possible to analyze the topology sensitivity of a fault mechanism, complicated preparation involving opening of the memory chip package is necessary. Preparation of this type entails the risk of the chip possibly being destroyed and as a result no longer being available for further analysis.